1. Field of the Invention
The present invention relates to a video decoding system, and more particularly, to a frame memory access controller of an MPEG-2 video decoding system used for a digital broadcasting receiver or a digital video conference system.
2. Discussion of the Related Art
The MPEG-2 technique has been adopted as a video compression standard for digital broadcasting currently prepared and serviced worldwide. Accordingly, a digital broadcasting receiver must be equipped with an MPEG-2 video decoding system.
In order to decode and display a high definition (HD) video or support various data broadcasts by the video decoding system, a processing speed of a video decoding chip must be increased. Accordingly, the video decoding system uses an external memory, such as a synchronous dynamic random access memory (SDRAM) or a double data rate (DDR) SDRAM.
For the HD video decoding, the external memory must include a memory area for a bit buffer and another memory area for storing decoded frames. Specifically, a memory space of about 10 through 13 Mbytes is used for storing the decoded frames.
However, when various memory access units (MAU) share the external memory, there is required a method for reducing the frequency and time of access of the external memory by the video decoding system.